The Intel XScale microarchitecture is a high-performance, ultra-low power microarchitecture. It is compliant with the ARM Version 5TE ISA instruction set (excluding the floating point instruction set).
The microarchitecture surrounds the ARM compliant execution core with Instruction and Data Memory Management Units; Instruction, Data and Mini-Data Caches; Write, Fill, Pend and Branch Target Buffers; Power Management, Performance Monitoring, Debug and JTAG Units; Coprocessor Interface; MAC Coprocessor; and Core Memory Bus.
IAR Embedded Workbench® for ARM provides device support on these levels:
Core support
Instruction set support in compiler, assembler, linker and debuggers
Header/DDF files
Peripheral register names in C/assembler source and debugger as well as device setup configuration files
Flash loader
For on-chip flash or off-chip EVB flash
Project examples
Varies from simple to fairly complex applications