Master’s Thesis Proposal: Testing C/C++ atomic operations

Master’s Thesis Proposal:
Testing C/C++ atomic operations

Target Audience

For you with a deep interest in applied parallelism and concurrent programming.


Correctness is cruical in embedded systems. Today’s embedded processers are increasingly parallel. To ensure parallel correctness of a program written in a high level language, three main components can be discerned:

  • The memory model of an instruction set architecture (ISA) describes how (concurrent/parallel) accesses to shared memory will be ordered, and thus describes in which order instructions has to occur in a parallel program to ensure correct behavior.
  • Modern programming language standard’s, such as C11/C++11 (henceforth collectively denoted C11), define a memory model of their own, giving the programmer guarantees on the program behavior.
  • The compiler should ensure that correctness is maintained when translating the C11 memory model to the ISA memory model of some concrete architecture.

The task

The task is to outline a tool for stress-testing and detecting errors in a compiler’s translation from the memory model of C11 to the memory model of an ISA, specifically focusing on testing the implementation of atomic operations. It must be possible to use the tool barebone (without a supporting operating system), typically on RISC-V and Arm architectures.

Some key concepts: threads and scheduling, litmus testing, embedded systems…and more.

Some relevant links, similar to this proposal, but without a focus on embedded systems 


Does this sound ineteresting? Please contact Susanne Dahlén, Director of Engineering IAR Systems

Mobile: +46 708 66 10 76

© IAR Systems 1995-2020 - All rights reserved.

We use cookies on this website to provide you with a better experience. You need to accept cookies to continue using this site. Cookies