IAR Systems and Andes collaborate to boost performance for RISC-V users
Uppsala, Sweden and Hsinchu, Taiwan—November 29, 2018—IAR Systems®, the future-proof supplier of software tools and services for embedded development, and Andes, the prominent CPU IP provider, announce that they have formed a partnership in order to deliver powerful development tools for Andes’ RISC-V-based solutions.
IAR Systems provides the C/C++ compiler and debugger toolchain IAR Embedded Workbench®. The toolchain offers leading code performance for size and speed, as well as extensive debug functionality with a fully integrated debugger with simulator and hardware debugging support. Since 1983, IAR Systems’ solutions have ensured quality, reliability and efficiency in the development of over one million embedded applications. The strong technology offering is accompanied by IAR Systems’ renowned technical support and services.
Andes Technology Corporation is a leading embedded processor intellectual property supplier. Since 2005, the company develops high-performance, low-power processors and their associated SoC platforms, and they have created a rich series of 32-bit embedded CPU core families with a record of more than 2.5 billion accumulated units of Andes-Embedded SoC shipped globally by end of 2017. Andes provides the RISC-V cores, AndesCore™ N25(F)/NX25(F) and A25/AX25, with AndeStar™ V5 instruction extension and leading Andes Custom Extension™ (ACE) instruction customization capabilities. The AndesCore families are being used for a wide range of smart emerging applications including satellite navigation, high-precision sensor fusion, advanced smart meters, smart wireless communication, networking, voice processing, ADAS, storage, and machine/deep learning. To further boost the performance in the target applications, and to ensure code density, Andes and IAR Systems collaborate to support the cores in IAR Embedded Workbench.
“Andes is moving heavily into RISC-V, and we are determined to support their efforts,” says Anders Holmberg, Chief Strategy Officer, IAR Systems. “By providing maximized code speed and minimized code size for Andes powerful RISC-V cores, we will create new possibilities to reduce time to market and ensure high quality applications based on Andes’ RISC-V ISA.”
“We are excited to partner with IAR Systems to bring new capabilities to the RISC-V community,” comments Dr. Charlie Su, CTO and Senior VP, Andes Technology Corporation. “Together, we will offer powerful solutions for Andes V5 extended ISA as well as ACE that will enable our customers to meet the demanding requirements of today's electronic devices.”
Support for Andes cores will be provided in IAR Embedded Workbench for RISC-V. The toolchain is currently under development and the first version will be available in mid-2019.
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