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This article briefly describes the Renesas RH850 multicore MCU and how IAR Embedded Workbench for RH850 is dealing with it.
RH850 comes as a Symmetric multicore (SMP) meaning that the target has two or more identical CPUs on the same physical chip. The block diagram below describes RH850/F1H which is a dual core MCU.
RH850/F1H (Dual Core) block diagram
Each CPU has a high-speed accessible Local RAM. In addition there is a common Global RAM for data sharing among the CPUs. A part of the global RAM area works as a retention RAM which means that the content is retained as long the power supply voltage does not fall below a certain limit. The Code Flash memory is included for program storage. All cores share the code flash and are connected to it via a so called Flash interface. The Data flash is a shared rewritable flash memory that allows a higher number of rewrites than the code flash memory.
For a dual-core device like RH850/F1H, two programs that would be executed by two separate single-core devices can be executed by separate cores in a multicore device. Basically, the two programs are executed independently in each core without interfering with each other. If data needs to be passed between the two programs, both cores have access to the global RAM. As instruction-fetch is supported in the global RAM, function sharing is allowed also in RAM. By default, each core also has its own C stack located in the local RAM.
In the IAR Embedded Workbench startup routine (cstartup), all cores initialize their own system registers and the variables located in their own local RAM. Core 1 (PE1) will also initialize all global RAM areas and the C++ constructors while the other cores wait for it to complete. The synchronization is handled by using the Exclusive Control Register 0 (G0MEV0) as a semaphore. Each core can optionally handle its own low-level initialization in the __low_level_init routine which is called from cstartup with a parameter telling which CPU core that is calling it.
By default, all cores in an RH850 multicore system have its own interrupt vector table. If one or more cores need to specify their own specific interrupt functions, #pragma core is used. Example:
#pragma core = 2 // PE2-specific ISR
#pragma vector = INTDMA0_vector
__interrupt void dma( void )
The RH850 symmetric multicore can be accessed through a single Renesas E1 or E20 on-chip debug probe. The C-SPY debugger supports SMP debugging within one single instance of the IAR Embedded Workbench IDE and at any given time, the different debugger windows show the state of one of the cores—the one in focus. The following apply for multicore debugging:
The Cores window is available from the View menu and shows a list of all available cores, and gives some information about each core’s execution state.
The line highlighted in bold is the core currently in focus, which means that any window showing information that is specific to a core will be updated to reflect the state of the core in focus.
IAR Embedded Workbench incorporates all the parts you need to successfully initialize a RH850 multicore system, implement your software modules to benefit from the extra computing power that a multicore system brings and finally, seamlessly debug your application.
This article is written by Micael Borgefeldt, Product Manager at IAR Systems.