Handling unaligned accesses that leads to a 'Usage Fault' or 'Hard Fault' exception

Technical Note 58203



9/11/2015 2:22 PM


This technical note describes actions to take when an unaligned access leads to a ‘Usage Fault’ or ‘Hard Fault’ exception.

This technical note applies to devices based on the ARMv7-M or ARMv8-M architecture.

(For other architectures, see below.)


There are two different suggestions for avoiding exceptions:

  • Let the application clear the 'UNALIGN_TRP' bit (or avoid setting the bit), in the Configuration and Control register.
  • Compile the application with the option --no_unaligned_access.

The first suggestion makes the device accept unaligned accesses. When the device is set up in this manner, the IAR C/C++ Compiler™ can generate more efficient code. The runtime library is built to take advantage of this.

The second suggestion is for when the 'UNALIGN_TRP' bit is set by the application. In this situation the linker will redirect affected library functions to function variants that handle the unaligned accesses. These variants are less efficient.


The devices based on the ARMv7-M or ARMv8-M architecture can take advantage of this technical note:

  • Examples of ARMv7-M architectures are Cortex-M3, Cortex-M4 and Cortex-M7.
  • The Cortex-M0, Cortex-M0+ and Cortex-M1 cannot take advantage of this technical note as they are based on the ARMv6-M architecture.
  • Other examples of devices, not covered by this technical note, are those that are based on the ARM7 and ARM9 architectures.

More information can be found in your hardware documentation, for example, ‘4.3.9. System Handler Control and State Register’ in ‘Cortex-M3 Devices Generic User Guide’ and in ‘4.3.6. Configuration and Control Register’ in ‘Cortex-M0 Devices Generic User Guide’.

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