This technical note describes actions to take when an unaligned access leads to a ‘Usage Fault’ or ‘Hard Fault’ exception.
This technical note applies to devices based on the ARMv6 (excluding ARMv6-M), ARMv7-M, and ARMv8-M architectures. For other architectures, especially the ARMv6-M, see the heading ‘Other architectures’ below.
These are two different suggestions for avoiding exceptions:
This makes the device accept unaligned accesses. When the device is set up in this manner, the IAR C/C++ Compiler™ can generate more efficient code. The runtime library is built to take advantage of this.
The first suggestion makes the device accept unaligned accesses. When the device is set up in this manner, the IAR C/C++ Compiler™ can generate more efficient code. The runtime library is built to take advantage of this.
This suggestion is applicable when the 'UNALIGN_TRP' bit is set by the application. In this situation, the linker will redirect affected library functions to function variants that handle the unaligned accesses. These variants are less efficient.
This technical note isn’t applicable to devices based on the ARMv4, ARMv5, and ARMv6-M architectures.
Devices based on the ARMv6, ARMv7-M, and ARMv8-M architectures can take advantage of this technical note. (Examples of ARMv7-M architectures are Cortex-M3, Cortex-M4 and Cortex-M7)
More information can be found in your hardware documentation, for example, ‘4.3.9. System Handler Control and State Register’ in ‘Cortex-M3 Devices Generic User Guide’ and ‘4.3.6. Configuration and Control Register’ in ‘Cortex-M0 Devices Generic User Guide’.
All product names are trademarks or registered trademarks of their respective owners.