Getting started with 64-bit RISC-V cores in IAR Embedded Workbench

In this short video, you will get an overview on how to get started with RV64 RISC-V cores and the RV64I base instruction set in IAR Embedded Workbench for RISC-V. You will learn what settings are required to start your first 64-bit RISC-V project, including the core selection, the linker configuration, debug setup and more. Additionally we will explore the features included in the latest releases including the following highlights:

 

• Support for 64-bit core (RV64) and also various RV64 devices from Andes, Codasip, Microchip, Nuclei and SiFive

• Library support for the C++17 language standard (Libc++)

• Support for RV64 cores in the simulator and hardware debugger

• SMP multicore debug support in I-jet

• Editor enhancements with window color themes (including dark mode) and syntax feedback

• Cross-platform IAR Build Tools for automated workflows

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