Developing bare-metal applications based on 64-bit RISC-V cores

For many smart applications, using an Embedded Linux OS would be an overkill and deliver less performance. In this session, we will cover the elements of creating a bare-metal application from scratch for RV64 (64-bit) RISC-V cores. We will focus on the initial setup and configuration, startup, memory mapping, and tune the speed optimizations for bare-metal applications.

In addition, we will demonstrate the extensive debugging and analysis possibilities of the latest IAR Embedded Workbench for RISC-V with RV64 (64-bit) support, such as complex code and data breakpoints, runtime stack analysis, call stack visualization, code coverage analysis for improving the multicore development and distributing the load of the bare-metal application.

This session is recommended for all developers who are starting with RV64 (64-bit) RISC-V cores or existing adopters that want to make a technology switch as smooth and efficient as possible.