Live Event
IAR at embedded world North America 2026
Meet IAR at the third edition of embedded world North America, a three-day tradeshow and technical conference exploring the latest in embedded systems technology.
Visit us at Booth 5502 to experience the interactive demo of IAR’s end-to-end embedded development platform, meet with our embedded development experts, and discuss your project challenges and goals. Plus, join our technical sessions covering topics including edge AI, RISC-V, and designing for long-term compliance.
Use discount code IAR26541 to save $40 an Expo Hall or Full Conference pass.
Date: September 22-24, 2026
Location: Anaheim Convention Center, Anaheim, CA
Register: https://embedded-world-na.com/
Technical Sessions:
You Will Be Maintaining This Firmware for 10+ Years: Design Your Pipeline Accordingly
Tuesday, September 22 | 11:00 AM - 11:25 AM | Room 201AB
The embedded industry is entering a new era of regulatory accountability. Regulations such as the EU Cyber Resilience Act are forcing product teams to think beyond launch and consider the full operational lifecycle of their devices, including how vulnerabilities will be patched, how software bills of materials will be maintained, and how compliance will be demonstrated years after initial certification.
This session is motivated by the practical reality that most embedded teams design their pipelines for the sprint to production, not for the decade that follows. Long-lived devices in industrial, medical, automotive, and IoT domains require a fundamentally different approach to build traceability, toolchain stability, and automated security checks.
The intended audience is embedded engineers, security architects, compliance managers, and engineering leaders responsible for products with multi-year field lifetimes, particularly in regulated industries.
Edge AI Is Easy to Demo and Hard to Ship: Toolchains Decide Who Succeeds
Tuesday, September 22 | 1:55 PM - 2:20 PM | Room 202
Edge AI has become one of the most discussed topics in embedded development, yet the gap between a working demo and a production-ready deployment remains poorly understood. Most conference content focuses on models, frameworks, and benchmarks, but the engineering teams that actually ship these products face a different set of problems: toolchain limitations, memory constraints, and the near-total lack of observability once the model runs on real hardware.
This session addresses the production side of edge AI, the part that rarely gets talked about. It focuses on what happens after the model is chosen: how compiler optimizations, memory tuning, and debugging workflows determine whether a product ships on time and stays maintainable over its lifecycle.
The intended audience is embedded engineers, engineering managers, and product managers who are evaluating or actively working on edge AI deployments on constrained targets such as microcontrollers and low-power MPUs.
Closing the Hardware–Software Gap in FPGA Based RISC V Systems
Wednesday, September 23 | 11:00 AM - 11:25 AM | Room 203
FPGA-based RISC-V systems offer significant architectural flexibility, enabling teams to tailor processor configurations, memory subsystems, and peripherals to application-specific needs. In soft-core designs, however, this flexibility comes at a cost: hardware and software are tightly coupled, and misalignment between the two frequently surfaces during software bring-up and system validation.
Many projects move quickly through hardware generation but slow down dramatically once software enters the picture. Changes to memory architecture or peripheral configuration can directly impact software correctness, leading to inefficient debug cycles, limited observability, and late-discovered integration issues. This session addresses the need for workflows that reduce friction between hardware creation and software validation.
The intended audience is embedded software engineers, FPGA developers, and system architects working with soft-core RISC-V platforms, particularly those involved in software bring-up, system integration, and debugging. Prior embedded experience is helpful, deep RISC-V or FPGA implementation knowledge is not required.
