IAR at Microchip MASTERs 2026

Meet IAR at Microchip's annual premier in-person learning event designed to enhance your skills through comprehensive courses, hands-on workshops, and expert-led sessions.

Join our Technical Sessions on Monday, 8/10 and Tuesday, 8/11 evenings, where we’ll dive into topics including RISC-V, CRA, and edge AI.

Plus, we’ll be at Innovation Night on Tuesday, 8/11 from 7 PM – 10 PM. Then, you can find our Partner Booth in the conference foyer on Wednesday, 8/12 from 10 AM – 7 PM. Visit us for an interactive demo of IAR’s end-to-end embedded development platform, meet our embedded development experts, and discuss your project challenges and goals.
 

Dates: August 10-13, 2026

Location: JW Marriott Phoenix Desert Ridge Resort & Spa (Phoenix, AZ)

Register: https://events.microchip.com/event/1954260d-15f6-463d-92ea-f336f7c24453/summary

 

Technical Sessions

Your RISC-V Core Is Ready. Your Software Workflow Isn't.
Monday, August 10  |  7:30 PM   |  Room Wildflower A

Soft-core RISC-V on an FPGA gives you something rare in embedded development: a processor you can actually change. Custom memory maps, bespoke peripherals, pipeline tweaks tuned to your workload. The hardware side of that story has never been easier to tell. The software side is where projects quietly fall apart.

When the processor is defined in RTL and the software stack has to catch up, the gap between "hardware is ready" and "software is running correctly" can swallow months. Memory architecture changes break assumptions the toolchain made last week. Peripheral configurations shift and nobody told the debugger. Integration issues that should have surfaced at bring-up show up instead during system validation — when the cost of finding them is highest.

This session is about closing that gap. We'll look at what modern toolchains and debug workflows can do to track a moving hardware target: how to maintain software correctness across configuration changes, how to get meaningful observability on a core you built yourself, and how to structure bring-up so that hardware and software validation happen in parallel rather than in sequence.

If you're bringing up software on a soft-core RISC-V platform — or designing one that someone else will have to debug — this session will change how you think about the handoff.

 

You Shipped It. Now You Own It for a Decade.
Tuesday, August 11  |  7:30 PM   |  Room Wildflower A

Congratulations — your firmware is in production. It's also running on hardware in the field that nobody will replace for ten years, in an industry that regulators are now watching very closely.

The EU Cyber Resilience Act isn't a future problem. It's a present one that most embedded teams are walking into with pipelines built entirely for the sprint to launch. No traceability past the release tag. Toolchain versions nobody can reproduce. Security checks that live in someone's head rather than in CI. SBOMs that don't exist yet and would take months to reconstruct.

That works fine until you need to patch a CVE in a device that's been in a medical cabinet or an industrial controller for six years. Then it doesn't work at all.

This session is about designing your pipeline for the product lifecycle you actually have, not the one that ends at first shipment. We'll cover what build traceability looks like when you need to defend it to a regulator, how toolchain stability and long-term support change your vendor decisions today, and how to layer automated security checks into a workflow that has to stay reproducible for the life of the product.

If you work on devices that will outlive your current job title — and in industrial, medical, automotive, and IoT, most of them will — this is the session that tells you what to build before you need it.

 

Your Edge AI Demo Lied to You
Tuesday, August 11  |  9:00 PM   |  Room Wildflower A

Everyone's seen the demo. Model runs, inference happens, numbers look great. Then the same code hits a real MCU with real memory constraints, a production compiler, and a shipping deadline — and none of it holds.

Edge AI is drowning in benchmarks and starving for production experience. The engineers actually shipping these products aren't struggling with model selection. They're fighting compiler behavior they can't predict, memory layouts that break at the last minute, and hardware that offers almost no visibility into what the model is actually doing at runtime.

This session skips the demo and goes straight to the hard part. We'll cover what happens after the model is frozen: how compiler optimization choices reshape inference performance and binary footprint, how memory tuning separates a product that ships from one that doesn't, and how modern debugging and tracing workflows can finally give embedded engineers the observability they've been missing on constrained targets.

If you're an embedded engineer, engineering manager, or product leader with an edge AI deployment on a microcontroller or low-power MPU — either in progress or on the roadmap — this session is the one the framework vendors won't give you.

 

Meet the Team

Shawn Prestridge, US Field Applications Engineer Manager

DeWayne Gibson, Senior Field Applications Engineer

Nick Pitruzzello, Account Manager