Functional safety, RISC-V, Automotive
Driving ASIL-grade innovation: Optimizing motor control performance and safety with Codasip and IAR
- By Niklas Källman and Laura Sartori
- 5 min read

- Computational intensity: Trigonometric calculations (sine, cosine) inherent in DQ0 transformations are computationally intensive. Executing these efficiently within tight real-time loops is critical for optimal motor performance, power consumption (PPA - Power, Performance, Area), and responsiveness.
- Safety and reliability: For ASIL B/D systems, the software must behave deterministically and safely under a range of foreseeable conditions, including fault scenarios. Any deviation can have catastrophic consequences, ranging from vehicle performance degradation to critical system failures.
- Software complexity: As motor control algorithms become more sophisticated, the underlying firmware grows in complexity with the risk of introducing errors and potential security vulnerabilities.
- Development efficiency: The pressure to innovate rapidly must be balanced with the stringent requirements of automotive certification. Development teams need tools that accelerate the process while ensuring compliance.
Maximizing performance through specialized hardware acceleration
In computationally intensive tasks like motor control, specialized hardware acceleration brings competitive advantage. Codasip’s new L735 and L739 RISC-V IP cores can be easily extended to provide hardware accelerators specialized for the automotive space. Accelerating the CORDIC function for a motor control use case is a prime example of the specialized hardware available for the new L735 and L739 automotive cores.
- The Codasip L735 and L739 processors deliver the high-performance and real-time features required to be a competitive alternative to the popular Arm Cortex-M7.
- The Codasip L735 processor can be integrated as a single core into a functional safety system requiring ASIL B integrity. The Codasip L739 processor, with its dual-core lockstep mechanism, can be used for applications up to ASIL D. The functional safety pack and certifications are available to support any automotive customer's integration efforts with these high-performance embedded cores.
- Both processors support Bounded Customization, allowing for the addition of domain-specific accelerators. By offloading these demanding computations to a CORDIC accelerator within Codasip L735 and L739 processors, motor control systems can achieve significant improvements in performance, power, and area (PPA). This can lead to a threefold increase in DQ0 algorithm performance with a negligible impact on the silicon area.
This combination of functional safety and domain-specific acceleration provides an optimized and flexible RISC-V solution that can keep in step with the state-of-the-art and meet quality and safety compliance objectives.
Accelerators, such as CORDIC, can be added and tailored using Codasip Studio or provided by Codasip as configurable options of the IP.
Leveraging IAR’s robust development platform for a streamlined certification process
Even the most performant hardware and optimized algorithms are insufficient without a development platform that streamlines the development and functional safety certification process. IAR's comprehensive development platform directly addresses the multifaceted challenges of developing safety-critical motor control applications.
- Robust code quality and efficiency
IAR’s build tools ensure that the motor control algorithms are translated into the most efficient machine code, allowing developers to leverage the fully optimized potential of the RISC-V ISA extensions. In addition, the toolchain’s code-size and memory-usage optimizations help developers meet the tight resources typical of real-time automotive ECUs. - Proactive safety and security with static code analysis
In safety-critical applications, discovering problems early is essential. IAR’s development platform performs compile-time analysis of your source code and flags potential defects, security weaknesses and violations of established coding standards such as CERT C, ISO/IEC TS 17961 (CWE-mapped rules), MISRA C (1998/2004/2012) and MISRA C++ 2008.
- Comprehensive debugging and runtime analysis
Static analysis is powerful, but dynamic testing and runtime analysis are equally crucial for ASIL B/D compliance. IAR's runtime analysis, profiling, code coverage and debugging provide a robust validation framework. This integrated approach allows developers to prove mission-critical code coverage and identify runtime anomalies.
For automated testing, IAR’s development platform offers seamless CI/CD integration. Whether you're testing on simulators or real hardware, you get clear pass/fail signals, comprehensive coverage metrics, and detailed profiling data automatically.
Conclusion: a great foundation for automotive innovation
The pairing of the ASIL B/D certified Codasip RISC-V cores, L735 and L739, enhanced with CORDIC acceleration, and the safety-certified IAR toolchain provides a great foundation for powerful, compliant motor control applications.